I perform research in the area of parallel computing with an emphasis on parallel programming and algorithms. I believe that for parallel computer systems to be practical they must be more efficient, easier to build and program, and easier to debug. I believe an important open question in today’s parallel computing research field is: how can we reduce the challenge of finding, fixing, or avoiding, concurrency bugs? Aside from transactional memory’s benefit of altogether avoiding such bugs, I believe the current state-of-the-art answers to this question are insufficient for non-expert parallel programmers.
I am primarily a research scientist in the Programming Systems Lab at Intel Labs, Intel Corporation. I also hold an appointment as an assistant professor adjunct at the University of Colorado-Boulder in the department of Electrical, Computer, and Energy Engineering. For over a decade, I have run my own software company, Nodeka, LLC., of which I am the founder and CEO.
At Intel, I spend my days researching transactional memory and multithreaded programming and debugging. I am interested in all aspects of parallel systems (e.g., hardware, software, designing, coding, testing, debugging), machine learning, and algorithms. I am an editor and active member of the committee for the Draft Specification for Transactional Memory Constructs in C++.
Latest News
2012-05-08: We gave our second technical specification presentation for transactional memory at the C++ Concurrency Study Group meeting in Seattle. The result of the talk has led to the creation of study group 5 (SG5) with the specific intent of resolving outstanding issues with the Draft Specification of Transactional Language Constructs for C++ such that it (or some subset of it) can be accepted as a technical specification for C++. The slides for our talk can be found here.
2012-03-28: Our submission, Concurrent Predicates: Finding and Fixing the Root Cause of Concurrency Violations, has been accepted to HotPar’12.
2012-02-08: We gave our technical report presentation to the Standard C++ Committee on Transactional Language Constructs for C++. It can be found here.
2012-02-04: We, the TM Specification Drafting Group, have released version 1.1 of Draft Specification of Transactional Language Constructs for C++.
2012-01-13: We have submitted a technical report proposal to integrate transactional memory into Standard C++. It can be found here.
2011-12-10: Our Intel invention disclosure, the second in a series on technology that simplifies the debugging of parallel software, by Youfeng Wu, Justin Gottschlich, Gilles Pokam, Shiliang Hu, and Ali-Reza Adl-Tabatabai, has been approved by Intel’s Technical Review committee for patent application filing.
2011-11-3: I am on the program committee for TRANSACT’12. Please consider submitting a paper by the December 1, 2011, submission deadline.
2011-10-8: Our demonstration of new techniques to debug parallel software at Intel’s Software Professionals Conference was awarded the “Best Demonstration Award.”
2011-9-16: Our Intel invention disclosure which aims to simplify the debugging of parallel software, by Justin Gottschlich, Gilles Pokam, Cristiano Pereira, and Jungwoo Ha, received top ranking from Intel’s Technical Review committee and has been approved for patent application filing.
Selected Publications
Concurrent Predicates: Finding and Fixing the Root Cause of Concurrency Violations (BibTex)
Justin E. Gottschlich, Gilles Pokam, and Cristiano Pereira
[USENIX Workshop on Hot Topics in Parallelism (HotPar), June 2012]
CoreRacer: A Practical Memory Race Recorder for Multicore x86 TSO Processors (21% acceptance, 44/209) (BibTex)
Gilles Pokam, Cristiano Pereira, Shiliang Hu, Ali-Reza Adl-Tabatabai, Justin E. Gottschlich, Jungwoo Ha, and Youfeng Wu
[International Symposium on Microarchitecture (MICRO), December 2011]
Programming with Concurrent Predicates (47% acceptance rate, 313/661) (Winner Best Demonstration Award)
Justin E. Gottschlich, Cristiano Pereira, Gilles Pokam, and Jungwoo Ha
[Intel Software Professionals Conference, October 2011]
Optimizing the Concurrent Execution of Locks and Transactions (37% acceptance, 19/52) (BibTex)
Justin E. Gottschlich and JaeWoong Chung
[International Workshop on Languages and Compilers for Parallel Computing (LCPC), September 2011]
An Efficient Software Transactional Memory Using Commit-Time Invalidation (41% acceptance, 29/70) (Winner Best Presentation Award) (BibTex)
Justin E. Gottschlich, Manish Vachharajani and Jeremy G. Siek
[IEEE/ACM International Symposium on Code Generation and Optimization (CGO), April 2010]
Extending Contention Managers for User-Defined Priority Based Transactions (BibTex)
Justin E. Gottschlich and Daniel A. Connors
[ACM Workshop on Exploiting Parallelism with Transactional Memory and other Hardware Assisted Methods (EPHAM). In conjunction with CGO. April 2008]
DracoSTM: A Practical C++ Approach to Software Transactional Memory (BibTex) (52% acceptance, 11/21)
Justin E. Gottschlich and Daniel A. Connors
[ACM SIGPLAN Symposium on Library-Centric Software Design (LCSD). In conjunction with OOPSLA. October 2007]